Hello,   I have some hard time working on the eth_mac_latest opencore project, WISHBONE compatible. I can not make it function well. after much strugle I managed to make it send data as fixed UDP packets. I get the packet through Wireshark. I use one RX_RAM and one TX_RAM. I have noticed the following intermittent (this happens 50% of the time) behaviour. The received packets have some discrepency I have 8 bytes that are repeated (indes is  with respect to the 1st byte in the preamble):

Bytes : 59th,    58th,    57th,     56th (OK)
Bytes : copy_59  copy_58  copy_57 copy_56

Bytes : 64th,    65th,    66th,     67th  (4 bytes received OK)
Bytes : copy_64  copy_65  copy_66 copy_67 (4 bytes repeated)

I am not sure where the problem is. Could be a bug in the core ?? Or am I missing something.

If I understand well the signals of the Wishbone :
When I need to set the length of the frame to be sent I do ;
Initial state :
mb_wb_ack_i  = 1  (Master wishbone aknolwledge input)

S2*** write to the TX_BD_0 ***** index 0
wb_we_i = 1  ( write enable)
wb_cyc_i = 1 (write ccyle in progress)
wb_stb_i = 1 (strobe input)
wb_adr_i = 0x100 (address of the TX_BD)
wb_sel_i = 0xF   (full bus width)
wb_dat_i = LENGTH_OF_FRAME (input of the slave wishbone)

S3*** write to the TX_BD_4 ***** inex 4,  TXPOINTER = 0
wb_we_i = 1  ( write enable)
wb_cyc_i = 1 (write ccyle in progress)
wb_stb_i = 1 (strobe input)
wb_adr_i = 0x104 (base address of the TX_BD + 4)
wb_sel_i = 0xF   (full bus width)
wb_dat_i = 0x0 (input of the slave wishbone)

S3*** write to the MODER ***** TXEN = 1
wb_we_i = 1  ( write enable)
wb_cyc_i = 1 (write ccyle in progress)
wb_stb_i = 1 (strobe input)
wb_adr_i = 0x000 (address of the MODER)
wb_sel_i = 0xF   (full bus width)
wb_dat_i = 0x00A422 (input of the slave wishbone) TXEN = 1

*** done return to initial state

Do I have to set the mb_wb_ack_i ?? I have noticed that when I set the mb_wb_ack_i = 1 input inside my states I get weired results. Some times I lose parts of the preamble.
Normally, the m_wb_ack_i is set after a successful termination of a master wishbone read cyle. This happens when the master wishbone reads frame from memory. But this happens by the core itself. This is automatically activated atfer the TXEN bit is enabled. My question is could the m_wb_ack_i be named wrong ?? Could it be for the slave wishbone and should be renamed as wb_ack_i instead ??

The documentation says it is Acknowledge input (indicates a normal cycle trmination) is this clear enough ?? I do not think so. Are there other signals to take about in order to avoid clashes between receive and transmit ??
Your help is appreciated A.C